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1 fn6228.4 isl55110, isl55111 dual, high speed mosfet driver the isl55110 and isl55111 are dual high speed mosfet drivers intended for applications requiring accurate pulse generation and buffering. target applications include ultrasound, ccd imaging, au tomotive piezoelectric distance sensing and clock generation circuits. with a wide output voltage range and low on-resistance, these devices can drive a variety of resistive and capacitive loads with fast rise and fall times, allowing high speed operation with low skew, as required in large ccd array imaging applications. the isl55110 and isl55111 are compatible with 3.3v and 5v logic families and incorpor ate tightly controlled input thresholds to minimize the effect of input rise time on output pulse width. the isl55110 has a pair of in-phase drivers while the isl55111 has two drivers operating in antiphase. the isl55110 has a power-down mode for low power consumption during equipment standby times, making it ideal for portable products. the isl55110 and isl55111 are available in 16 ld exposed pad qfn packaging and 8 ld tssop. both devices are specified for operation over the full -40c to +85c temperature range. functional block diagram features ? 5v to 12v pulse magnitude ? high current drive 3.5a ? 6ns minimum pulse width ? 1.5ns rise and fall times, 100pf load ?low skew ? 3.3v and 5v logic compatible ? in-phase and anti-phase outputs ? small qfn and tssop packaging ? low quiescent current ? pb-free (rohs compliant) applications ? ultrasound mosfet driver ? ccd array horizontal driver ? automotive piezo dr iver applications ? clock driver circuits isl55110 and isl55111 dual driver vh oa ob in-a o o o o o in-b o o gnd o power down o vdd o hiz-qfn* *hiz available in qfn package only *isl55111 in-b is inverting * ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # isl55110irz 55 110irz -40 to +85 16 ld qfn l16.4x4a isl55110ivz 55110 ivz -40 to +85 8 ld tssop m8.173 isl55111irz 55 111irz -40 to +85 16 ld qfn l16.4x4a isl55111ivz 55111 ivz -40 to +85 8 ld tssop m8.173 notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plasti c packaged products employ special pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations). intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity lev el (msl), please see device information page for isl55110 , isl55111 . for more information on msl please see techbrief tb363. data sheet march 17, 2011 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2006-2008, 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
2 fn6228.4 march 17, 2011 pinouts isl55110 (16 ld qfn) top view isl55111 (16 ld qfn) top view isl55110 (8 ld tssop) top view isl55111 (8 ld tssop) top view 16 15 14 13 ob gnd vh oa 1 2 3 4 12 11 10 9 vdd enable pd in-b 5678 in-a nc nc nc nc nc nc nc 16 15 14 13 ob gnd vh oa 1 2 3 4 12 11 10 9 vdd enable pd in-b 5678 in-a nc nc nc nc nc nc nc 6 7 8 5 1 2 3 4 vdd pd in-b in-a ob vh oa gnd 6 7 8 5 1 2 3 4 vdd pd in-b in-a ob vh oa gnd pin descriptions 16 ld qfn 8 ld tssop pin function 1 1 vdd logic power. 10 6 vh driver high rail supply. 11 7 gnd ground, return for both vh rail and vdd logic supply. 3 2 pd power-down. active logic high places part in power-down mode. 2 - enable qfn packages only. provides high speed logic hi z control of driver outputs while leaving device logic power on. 5 4 in-a logic level input that drives oa to vh rail or ground. not inverted. 4 3 in-b, inb logic level input that drives ob to vh rail or ground. not inverted on isl55110, inverted on isl55111. 9 5 oa driver output related to in-a. 12 8 ob driver output related to in-b. 6 through 8, 13 through 16 - nc no connect. isl55110, isl55111
3 fn6228.4 march 17, 2011 absolute maxi mum ratings (t a = +25c) thermal information vh+ to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.0v vdd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5v vin_a, vin_v, pdn, enable . . . . . . (gnd - 0.5v) to (vdd + 0.5v) oa, ob. . . . . . . . . . . . . . . . . . . . . . . . . . .(gnd - 0.5) to (vh + 0.5v) maximum peak output current . . . . . . . . . . . . . . . . . . . . . . (300ma) esd rating human body model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kv operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c thermal resistance ja (c/w) jc (c/w) 16 ld (4x4) qfn package (notes 5, 6) 45 3.0 8 ld tssop package (notes 4, 7) . . . 140 46 maximum junction temperature (plastic package). . . . . . . +150c maximum storage temperature range . . . . . . . . . . . -65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. important note: all parameters having min/max specifications are guaranteed. typical values are for information purposes only. u nless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: t j = t c = t a notes: 4. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. 5. ja is measured in free air with the component mounted on a high ef fective thermal conductivity te st board with ?direct attach? fe atures. see tech brief tb379. 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. for jc , the ?case temp? location is taken at the package top center. recommended operating conditions parameter description conditions min typ max unit v h driver supply voltage 5 12 13.2 v v dd logic supply voltage 2.7 5.5 v t a ambient temperature -40 +85 c t j junction temperature +150 c dc electrical specifications v h = +12v, v dd = 2.7v to 5.5v, t a = +25c, unless otherwise specified. parameter description test conditions min (note 8) typ max (note 8) units logic characteristics vix_lh logic input threshold - low to high l ih = 1a: vin_a, vin_b 1.32 1.42 1.52 v vix_hl logic input threshold - high to low l il = 1a: vin_a, vin_b 1.12 1.22 1.32 v vhys logic input hysteresis vin_a,vin_b 0.2 v vih logic input high threshold pdn 2.0 vdd v vil logic input low threshold pdn 0 0.8 v vih logic input high threshold enable - qfn only 2.0 vdd v vil logic input low threshold enable - qfn only 0 0.8 v iix_h input current logic high vin_a,vin_b = vdd 10 20 na iix_l input current logic low vin_a, vin_b = 0v 10 20 na ii_h input current logic high pdn = vdd 10 20 na ii_l input current logic low pdn = 0v 10 15 na ii_h input current logic high enable = vdd (qfn only) 12 ma ii_l input current logic low enable = 0v (qfn only) -25 na isl55110, isl55111
4 fn6228.4 march 17, 2011 driver characteristics r ds driver output resistance oa, ob 3 6 i dc driver output dc current (>2s) 100 ma i ac peak output current design intent verified via simulation. 3.5 a voh to vol driver output swing range vh voltage to ground 3 13.2 v supply currents i dd logic supply quiescent current pdn = low 4.0 6.0 ma i dd-pdn logic supply power-down current pdn = high 12 a ih driver supply quiescent current pdn = low, no resistive load d out 15 a ih_pdn driver supply power-down current pdn = high 1 a dc electrical specifications v h = +12v, v dd = 2.7v to 5.5v, t a = +25c, unless otherwise specified. (continued) parameter description test conditions min (note 8) typ max (note 8) units ac electrical specifications v h = +12v, v dd = +3.6, t a = +25c, unless otherwise specified. parameter description test conditions min (note 8) typ max (note 8) units switching characteristics t r driver rise time oa, ob: cl = 100pf/1k 10% to 90%, voh - vol = 12v 1.2 ns t f driver fall time oa, ob: cl = 100pf/1k 10% to 90%, voh - vol = 12v 1.4 ns t r driver rise time oa, ob cl = 1nf 10% to 90%, voh-vol = 12v 6.2 ns t f driver fall time oa, ob cl = 1nf 10% to 90%, voh-vol = 12v 6.9 ns tpdr input to output propagation delay figure 2, load 100pf/1k 10.9 ns tpdf input to output propagation delay 10.7 ns tpdr input to output propagation delay figure 2, load 330pf 12.8 ns tpdf input to output propagation delay 12.5 ns tpdr input to output propagation delay figure 2, load 680pf 14.5 ns tpdf input to output propagation delay 14.1 ns tskewr channel-to-channel tpdr spread with same loads both channels figure 2, all loads <0.5 ns tskewf channel-to-channel tpdf spread with same loads both channels. figure 2, all loads <0.5 ns fmax maximum operating frequency 70 mhz tmin minimum pulse width 6 ns pden* power-down to power-on time 650 ns pddis* power-on to power-down time 40 ns ten* enable to enable time (hiz off) 40 ns tdis* enable to enable time (hiz on) 40 ns note: 8. compliance to datasheet limits is assured by one or mo re methods: production test, characterization and/or design. isl55110, isl55111
5 fn6228.4 march 17, 2011 isl55110 input input rise and fall times 2ns c l 4.7f 0.1f + output vh = 12v 10% 10% 90% t f 90% t r 0.4v 12v input +3v 0v output inx in figure 1. test circuit rise (t r )/fall(t f ) thresholds isl55110 input input rise and fall times 2ns c l 4.7f 0.1f + output vh = 12v 50% 50% 50% 50% tpdr tpdf 0.4v 12v input +3v 0v output oa and ob isls55110 in-x in output oa isls55111 50% 50% 12v 0v output ob isls55111 t skew r = tpdr chn1 - tpdr chn2 figure 2. test circuit propagation tpd delay isl55110, isl55111
6 fn6228.4 march 17, 2011 typical performance curves (see ?typical performance cu rves discussion? on page 11) figure 3. driver r on vs vh source resistance figure 4. driver r on vs vh sink resistance figure 5. r on vs v dd source resistance figure 6. r on vs v dd sink resistance figure 7. i dd vs v dd quiescent current figure 8. i dd vs v h @ 50mhz (no load) 7.0 6.3 5.6 4.9 4.2 3.5 2.8 2.1 1.4 0.7 0.0 345678910111213 v h , drive rail (v) +85c -40c r on vdd 3.6v -50ma +25c 7.0 6.3 5.6 4.9 4.2 3.5 2.8 2.1 1.4 0.7 0.0 345678910111213 v h , drive rail (v) r on +85c -40c vdd 3.6v +50ma +25c 4.00 3.66 3.33 2.66 2.33 2.00 2.5 3.5 4.5 5.5 v dd (v) vh 5.0v r on ( ) 50ma vh 12.0v 4.00 3.66 3.33 2.66 2.33 2.00 2.5 3.5 4.5 5.5 v dd (v) vh 12.0v r on ( ) 50ma vh 5.0v 5.0 4.6 4.2 3.8 3.4 3.0 2.5 3.5 4.5 5.5 v dd (v) i dd (ma) vh 5v and 12v 10 9 8 7 6 5 4 3 2 1 0 4812 i dd (ma) vdd 3.6v v h , drive rail (v) isl55110, isl55111
7 fn6228.4 march 17, 2011 figure 9. quiescent i h vs v h figure 10. i h vs v h @ 50mhz (no load) figure 11. i dd vs frequency (dual channel, no load) figure 12. ih vs frequency (dual channel, no load) figure 13. vih logic thresholds figure 14. vil logic thresholds typical performance curves (see ?typical performance cu rves discussion? on page 11) (continued) 100 90 80 70 60 50 40 30 20 10 0 4812 v h , drive rail (v) i h (a) v dd 3.6v 200 180 160 140 120 100 80 60 40 20 0 4812 v h , drive rail (v) i h (ma) v dd 3.6v 15.0 13.5 12.0 10.5 9.00 7.50 6.00 4.50 2.00 0.50 0.00 50m 66m 100m 124m 128m toggle frequency (hz) i dd (ma) v h 5.0v v dd 3.6v 200 180 160 140 120 100 80 60 40 20 0 50m 100m 128m toggle frequency (hz) 66m 124m i h (ma) vh 5.0v vdd 3.6v 1.5 1.4 1.3 1.2 1.1 1.0 2.5 3.5 4.5 5.5 vdd (v) -40c +85c logic (v) 1.5 1.4 1.3 1.2 1.1 1.0 2.5 3.5 4.5 5.5 vdd (v) logic (v) -40c +85c isl55110, isl55111
8 fn6228.4 march 17, 2011 figure 15. t r vs temperature figure 16. t f vs temperature figure 17. tpd r vs temperature figure 18. tpd f vs temperature figure 19. t r vs v dd figure 20. t f vs v dd typical performance curves (see ?typical performance cu rves discussion? on page 11) (continued) 10 9 8 7 6 5 4 3 2 1 0 -40 -10 +20 +50 +85 package temp (c) rise time (ns) v h 12.0v v dd 3.6v 330pf 680pf 10 9 8 7 6 5 4 3 2 1 0 -40 -10 +20 +50 +85 package temp (c) fall time (ns) v dd 3.6v v h 12.0v 680pf 330pf 20 18 16 14 12 10 8 6 4 2 0 -40 -10 +20 +50 +85 package temp (c) propagation delay (ns) v h 12.0v v dd 3.6v 680pf 330pf v h 12.0v v dd 3.6v 20 18 16 14 12 10 8 6 4 2 0 -40 -10 +20 +50 +85 package temp (c) propagation delay (ns) 680pf 330pf 10 9 8 7 6 5 4 3 2 1 0 2.5 3.5 5.5 v dd (v) rise time (ns) v h 12.0v 4.5 100pf/1k 330pf 680pf 1000pf 10 9 8 7 6 5 4 3 2 1 0 2.5 3.5 5.5 v dd (v) fall time (ns) vh 12.0v 4.5 1000pf 100pf/1k 680pf 330pf isl55110, isl55111
9 fn6228.4 march 17, 2011 figure 21. t r vs v h figure 22. t f vs v h figure 23. tpd r vs v dd figure 24. tpd f vs v dd figure 25. tpd r vs v h figure 26. tpd f vs v h typical performance curves (see ?typical performance cu rves discussion? on page 11) (continued) 12.0 10.8 9.6 8.4 7.2 6.0 4.8 3.6 2.4 1.2 0.0 36 12 v h (v) rise time (ns) v dd 3.3v 9 680pf 330pf 100pf/1k 1000pf 36 12 v h (v) fall time (ns) v dd 3.3v 9 10.8 9.6 8.4 7.2 6.0 4.8 3.6 2.4 1.2 0.0 12.0 680pf 330pf 100pf/1k 1000pf 20 18 16 14 12 10 8 6 4 2 0 2.5 3.5 v dd (v) propagation delay (ns) v h 12.0v 4.5 1000pf 5.5 100pf/1k 20 18 16 14 12 10 8 6 4 2 0 2.5 3.5 5.5 v dd (v) propagation delay (ns) v h 12.0v 4.5 1000pf 100pf/1k 20 18 16 14 12 10 8 6 4 2 0 36 12 v h (v) propagation delay (ns) v dd 3.3v 9 1000pf 100pf/1k 20 18 16 14 12 10 8 6 4 2 0 36 12 v h (v) propagation delay (ns) v dd 3.3v 9 1000pf 100pf/1k isl55110, isl55111
10 fn6228.4 march 17, 2011 figure 27. tskew r vs temperature figure 28. tskew f vs temperature figure 29. tskew r vs v dd figure 30. tskew f vs v dd figure 31. tskew r vs v h figure 32. tskew f vs v h typical performance curves (see ?typical performance cu rves discussion? on page 11) (continued) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -10 +20 +50 +85 package temp (c) tskewr (ns) v h 12.0v v dd 3.6v 330pf 680pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 -10 +20 +50 +85 package temp (c) tskewf (ns) v h 12.0v v dd 3.6v 330pf 680pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3.5 5.5 v dd (v) skew (ns) v h 12.0v 4.5 330pf 680pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 2.5 3.5 5.5 v dd (v) skew (ns) v h 12.0v 4.5 680pf 330pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 36 12 v dd (v) skew (ns) v dd 3.3v 9 680pf 330pf 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 36 12 v dd (v) skew (ns) v dd 3.3v 9 680pf 330pf isl55110, isl55111
11 fn6228.4 march 17, 2011 typical performance curves discussion r on the r on source is tested by placing the device in constant drive high condition and connec ting -50ma constant current source to the driver output. the voltage drop is measured from vh to driver output for r on calculations. the r on sink is tested by placing the device in constant driver low condition and connecting a +50ma constant current source. the voltage dr op from driver out to ground is measured for r on calculations. dynamic tests all dynamic tests are conduc ted with isl55110, isl55111 evaluation board(s) (isl55110_11eval2z). driver loads are soldered to the evaluation board. measurements are collected with p6245 active fet probes and tds5104 oscilloscope. pulse stimulus is provided by hp8131 pulse generator. the isl55110, isl55111 evaluation boards provide test point fields for leadless connection to either an active fet probe or differential probe. tp-in fields are used for monitoring pulse input stimulus. tp-oa/b monitor driver output waveforms. c 6 and c 7 are the usual placement for driver loads. r 3 and r 4 are not populated and are provided for user-specified, more complex load characterization. pin skew pin skew measurements are based on the difference in propagation delay of the two channels. measurements are made on each channel from the 50% point on the stimulus point to the 50% point on the dr iver output. the difference in the propagation delay for channel a and channel b is considered to be skew. both rising propagation delay and falling propagation delay are measured and report as tskewr and tskewf. 50mhz tests 50mhz tests reported as no load actually include evaluation board parasitics and a single tek 6545 fet probe. however no driver load components are installed and c 6 through c 9 and r 3 through r 6 are not populated. general the most dynamic measurements are presented in three ways: 1. over-temperature with a v dd of 3.6v and v h of 12.0v. 2. at ambient with v h set to 12v and v dd data points of 2.5v, 3.5v, 4.5v and 5.50v. 3. the ambient tests are repeated with v dd of 3.3v and v h data points of 3v, 6v, 9v and 12v. figure 33. isl55110/11eval2z evaluation board isl55110, isl55111
12 fn6228.4 march 17, 2011 detailed description the isl55110, isl55111 are dual high speed mosfet drivers intended for applicati ons requiring accurate pulse generation and buffering. target applications include ultrasound, ccd imaging, au tomotive piezoelectric distance sensing and clock generation circuits. with a wide output voltage range and low on-resistance, these devices can drive a variety of resistive and capacitive loads with fast rise and fall times, allowing high speed operation with low skew as required in large ccd array imaging applications. the isl55110 and isl55111 are compatible with 3.3v and 5v logic families and incorpor ate tightly controlled input thresholds to minimize the effect of input rise time on output pulse width. the isl55110 has a pair of in-phase drivers while the isl55111 has two drivers operating in antiphase. both inputs of the device have independent inputs to allow external time phasing if required. in addition to power mosf et drivers, the isl55110, isl55111 is well suited for other applications such as bus, control signal, and clock drivers on large memory of microprocessor boards, where the load capacitance is large and low propagation delays ar e required. other potential applications include peripheral power drivers and charge- pump voltage inverters. input stage the input stage is a high impedance input with rise/fall hysteresis. this means that the inputs will be directly compatible with both ttl and lower voltage logic over the entire vdd range. the user should treat the inputs as high speed pins and keep rise and fall times to <2ns. output stage the isl55110, isl55111 output is a high-power cmos driver, swinging between ground and vh. at v h = 12v, the output impedance of the inve rter is typically 3.0 . the high peak current capability of the isl55110, isl55111 enables it to drive a 330pf load to 12v with a rise time of <3.0ns over the full temperature range. the output swing of the isl55110, isl55111 comes within < 30mv of the v h and ground rails. application notes although the isl55110, isl55111 is simply a dual level-shifting driver, there are several areas to which careful attention must be paid. grounding since the input and the high current output current paths both include the ground pin, it is very important to minimize any common impedance in the ground return. since the isl55111 has one inverting input, any common impedance will generate negative feedback, and may degrade the delay times and rise and fall times. use a ground plane if possible or use separate ground returns for the input and output circuits. to minimize any common inductance in the ground return, separate the input and output circuit ground returns as close to the isl55110, isl55111 as possible. bypassing the rapid charging and discharging of the load capacitance requires very high current spik es from the power supplies. a parallel combination of capacitors which have a low impedance over a wide frequency range should be used. a 4.7f tantalum capacitor in parallel with a low inductance 0.1f capacitor is usually sufficient bypassing. output damping ringing is a common problem in any circuit with very fast rise or fall times. such ringing will be aggravated by long inductive lines with capacitive loads. te chniques to reduce ringing include: 1. reduce inductance by making printed circuit board traces as short as possible. 2. reduce inductance by using a ground plane or by closely coupling the output lines to their return paths. 3. use small damping resistor in series with the output of the isl55110, isl55111. although this reduces ringing, it will also slightly increase the rise and fall times. 4. use good bypassing techniques to prevent supply voltage ringing. power dissipation calculation the power dissipation equation has three components: quiescent power dissipation, power dissipation due to internal parasitics and power dissipation because of the load capacitor. power dissipation due to internal parasitics is usually the most difficult to accurately quantitize. this is primarily due to crow-bar current which is a product of both the high and low drivers conducting effectively at the same time during driver transitions. design goals always target the minimum time for this condition to exist. given that how often this occurs is a product of frequency, crowbar effects can be characterized as internal capacitance. lab tests are conducted with driver outputs disconnected from any load. with design verification packaging, bond wires are removed to aid in the characterization process. based on laboratory tests and simulation correlation of those results, equation 1 defines the isl55110, isl55111 power dissipation per channel: 1. where: 3.3ma is the quiescent current from the vdd. this forms a small portion of the total calculation. when figuring two pvdd3.3e-3 = 10pf vdd 2 f 135pf vh 2 ++ f + (eq. 1) cl vh 2 f (watts/channel) isl55110, isl55111
13 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn6228.4 march 17, 2011 channel power consumption, only include this current once. 2. 10pf is the approximate parasitic capacitor (inverters, etc.), which the v dd drives 3. 135pf is the approximate parasitic at the d out and its buffers. this includes the effect of the crow-bar current. 4. c l is the load capacitor being driven power dissipation discussion specifying continuous pulse rates, driver loads and driver level amplitudes are key in determining power supply requirements, as well as dissipation/cooling necessities. driver output patterns also impact these needs. the faster the pin activity, the greater the need to supply current and remove heat. as detailed in the ?power dissipation calculation? on page 12, power dissipation of the device is calculated by taking the dc current of the v dd (logic) and v h current (driver rail) times the respective voltages and adding the product of both calculations. the average dc current measurements of i dd and ih should be done while running the device with the planned v dd and v h levels and driving the required pulse activity of both channels at the desired operating frequency and driver loads. therefore, the user must address power dissipation relative to the planned operating conditions. even with a device mounted per notes 4 or 5 under thermal information, given the high speed pulse rate and amplitude capability of the isl55110, isl55111, it is possible to exceed the +150c ?absolute-maximum junction temp erature?. therefore, it is important to calculate the maximum junction temperature for the application to determine if operating conditions need to be modified for the device to remain in the safe operating area. the maximum power dissipation allowed in a package is determined according to equation 2: where: ?t jmax = maximum junction temperature ?t amax = maximum ambient temperature ? ja = thermal resistance of the package ?p dmax = maximum power dissipation in the package the maximum power dissipation actually produced by an ic is the total quiescent supply current times the total power supply voltage, plus the power in the ic due to the loads. power also depends on number of channels changing state and frequency of operation. the extent of continuous active pulse generation will greatly effect dissipation requirements. the user should evaluate various heat sink/cooling options in order to control the ambi ent temperature part of the equation. this is especially true if the user?s applications require continuous, high speed operation. a review of the ja ratings of the tssop and qfn package clearly show the qfn package to have bett er thermal characteristics. the reader is cautioned against assuming a calculated level of thermal performance in actual applications. a careful inspection of conditions in your application should be conducted. great care must be taken to ensure die temperature does not exceed + 150c absolute maximum thermal limits. important note: the isl55110, isl55111 qfn package metal plane is used for heat sinking of the device. it is electrically connected to the negative supply potential ground. power supply sequencing apply v dd , then v h . power up considerations digital inputs should never be open. do not apply slow analog ramps to the inputs. again, place decoupling as close to the package as possible for both v dd and especially v h . special loading with most applications, the user will usually have a special load requirement. please contact intersil for evaluation boards or to request a device characterization to your requirements in our lab. . p dmax t jmax - t amax ja -------------------------------------------- - = (eq. 2) isl55110, isl55111
14 fn6228.4 march 17, 2011 isl55110, isl55111 quad flat no-lead plastic package (qfn) micro lead frame pl astic package (mlfp) l16.4x4a 16 lead quad flat no-lead plastic package (compliant to jedec mo-220-vggd-10) symbol millimeters notes min nominal max a 0.80 0.90 1.00 - a1 - - 0.05 - a2 - - 1.00 9 a3 0.20 ref 9 b 0.18 0.25 0.30 5, 8 d 4.00 bsc - d1 3.75 bsc 9 d2 2.30 2.40 2.55 7, 8 e 4.00 bsc - e1 3.75 bsc 9 e2 2.30 2.40 2.55 7, 8 e 0.50 bsc - k0.25 - - - l 0.30 0.40 0.50 8 l1 - - 0.15 10 n162 nd 4 3 ne 4 3 p- -0.609 --129 rev. 2 3/06 notes: 1. dimensioning and tolerancing conform to asme y14.5-1994. 2. n is the number of terminals. 3. nd and ne refer to the number of terminals on each d and e. 4. all dimensions are in millimeters. angles are in degrees. 5. dimension b applies to the meta llized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or mark feature. 7. dimensions d2 and e2 are fo r the exposed pads which provide improved electrical and thermal performance. 8. nominal dimensions are prov ided to assist with pcb land pattern design efforts, see intersil technical brief tb389. 9. features and dimensions a2, a3, d1, e1, p & are present when anvil singulation method is used and not present for saw singulation. 10. depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (l1) maybe present. l minus l1 to be equal to or greater than 0.3mm.
15 fn6228.4 march 17, 2011 isl55110, isl55111 package outline drawing m8.173 8 lead thin shrink small outline package (tssop) rev 2, 01/10 notes: end view detail "x" typical recommended land pattern top view b a c plane seating 0.10 c 0.10 c b a h 3.0 0.5 4.40 0.10 0.25 +0.05/-0.06 6.40 0.20 c b a 0.05 0-8 gauge plane see detail "x" 0.90 +0.15/-0.10 0.60 0.15 0.09-0.20 6 3 4 2 4 1.00 ref 0.65 1.20 max 0.25 0.05 min 0.15 max (5.65) (0.65 typ) (0.35 typ) (1.45) 1 c l pin 1 id mark 4 5 8 package body outline side view 2. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall 3. dimension does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.15 per side. 4. dimensions are measured at datum plane h. not exceed 0.15 per side. 5. dimensioning and toleranc ing per asme y14.5m-1994. 6. dimension on lead width does not include dambar protrusion. allowable protrusion shall be 0.08 mm total in excess of dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm. 7. conforms to jedec mo-153, variation ac. issue e dimensions in ( ) for reference only. 1. dimensions are in millimeters.

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